1. Field of the Invention
The present invention relates to a semiconductor storage device which comprises an array of memory cells, each memory cell consisting mainly of a variable resistor element of which the electric resistance is varied to save a data, arranged in rows and columns at a cross point mode where each row of the memory cells are connected at one end to a common data line and each column of the memory cells are connected at the other end to a common bit line. Particularly, the present invention relates to a semiconductor storage device which comprises a memory cell array of a cross point type where each variable resistor element is varied in the resistance by application of electric pulses.
2. Description of the Related Art
As known (and disclosed, for example, in “An Access-Transistor-Free (0T/1R) Non-Volatile Resistance Random Access Memory (RRAM) Using a Novel Threshold Switching, Self-Rectifying Chalcogenide Device”, by Y. Chen et al, IEDM Technical Digest, Session 37.4, 2003 which will be defined as Citation 1), semiconductor storage devices of a cross point type have been introduced where each memory cell in the memory cell array includes a storage device but not any selectable element and is connected to a data line (a selected row line) and a bit line (a selected column line) and will hence be referred to as a cross point memory hereinafter.
Such a known cross point memory has a variable resistor element located at the intersection (cross point) between a data line and a bit line in the memory cell array and connected at one of its lower and upper electrodes to the data line and at the other to the bit line thus to develop a memory cell. For example, the memory cell of Citation 1 is made of a chalcogenide material of which the resistance is varied by application of electric pulses, thus forming a variable resistance type non-volatile memory (TF-RRAM).
In Citation 1, the method of applying a write voltage between the data line and the bit line for writing a data on a target memory cell in the memory cell array is selected between ½ bias mode and ⅓ bias mode. FIGS. 12 and 13 schematically illustrate actions of the ½ bias mode and the ⅓ bias mode respectively for applying a voltage between the data line and the bit line in the memory cell array of a five-row and five-column matrix.
Referring to FIG. 12, the ½ bias mode permits the selected data line and the selected bit line to be applied with a row selecting potential (e.g., Vw) and a column selecting potential (e.g., 0 V) respectively for applying a bias voltage or write voltage Vw (=Vw−0V) to a variable resistor element of the target memory cell (denoted by the circle). Simultaneously, for inhibiting the unselected memory cells, which are not to be written, from being applied with the write voltage Vw (=Vw−0V), their unselected data lines and bit lines not connected with the target memory cell are applied with an intermediate voltage Vw/2 which is equal to a half the write voltage Vw on the basis of the selected bit line. More particularly, particular ones of the unselected memory cells which are connected with the selected data line and the selected bit line but not to be written are positively applied with the intermediate voltage which is too low to execute the writing action. As the ½ bias mode permits the intermediate voltage (equal to a half the write voltage Vw) to be applied to particular ones (denoted by the symbols ⋄) of the unselected memory cells which are connected with the selected data line and also particular ones (denoted by the symbols ⋄) of the unselected memory cells which are connected with the selected bit line, it will undesirably generate bias currents which thus increases the flows of current along both the selected data line and the selected bit line. FIG. 14 is an equivalent circuitry diagram schematically showing an action of the ½ bias mode where the write current runs through the target memory cell while undesired bias currents run through the unselected memory cells in a memory cell array of m rows by n columns (m and n being any natural numbers).
Referring to FIG. 13, the ⅓ bias mode permits the selected data line and the selected bit line to be supplied with a row selecting potential (e.g., Vw) and a column selecting potential (e.g., 0 V) respectively for applying a bias voltage or write voltage Vw (=Vw−0V) to a variable resistor element of the target memory cell (denoted by the circle). Simultaneously, for inhibiting the unselected memory cells, which are not to be written, from being applied with the write voltage Vw (=Vw−0V), their unselected data lines not connected with the target memory cell are supplied with a voltage Vw/3 which is equal to one third the write voltage Vw on the basis of the selected bit line and their unselected bit lines not connected with the target memory cell are supplied with another voltage 2Vw/3 which is equal to two third the write voltage Vw. More particularly, all the unselected memory cells which are not to be written are positively applied with a bias voltage (|Vw/3|) which is too low to execute the writing action to avoid its reception of the write voltage Vw. As the ⅓ bias mode permits the low bias voltage (equal to one third the write voltage Vw) to be applied to the unselected memory cells (denoted by the symbols ⋄) which are connected with the selected data line and the selected bit line and the other unselected memory cells connected with either the unselected data line or the unselected bit line, it will undesirably generate bias currents in the unselected memory cells, thus increasing the flows of current throughout the memory cell array. Meanwhile, the ⅓ bias mode is lower in the bias voltage applied to each of the unselected memory cells than the ½ bias mode. Since the number of the unselected memory cells which is applied with the bias voltage is greater in the ⅓ bias mode, the flows of current throughout the memory cell array will thus be increased proportionally. However, the bias voltage applied to the unselected memory cells connected with the selected data line and the selected bit line is lower than that of the ½ bias mode, the current running in the selected data line or the selected bit line will remain smaller than that of the ½ bias mode. FIG. 15 is an equivalent circuitry diagram schematically showing an action of the ⅓ bias mode where the write current runs through the selected memory cell while undesired bias currents run through the unselected memory cells in a memory cell array of m rows by n columns (m and n being any natural numbers).
FIG. 16 is a circuitry diagram showing an arrangement of data line selecting transistors TD0 to TD4 and bit line selecting transistors TB0 to TB4 connected with the data lines and the bit lines for applying the row selecting potential (Vw), the column selecting potential (e.g., 0 V), and the intermediate voltage (Vw/2) for inhibiting the writing action to each data line and bit line in the memory cell array supplied with voltages at the ½ bias mode shown in FIG. 12. The number of the data lines and the number of the bit lines may arbitrarily be determined. For example, the memory cell array includes a matrix of m rows by n columns (m and n being any natural numbers). The memory cell array shown in FIG. 16 has five rows and five columns.
In the writing action, the current Ids running in the selected data line (DL2 in FIG. 16) is a sum of the write current Iw running in the selected memory cell and the bias currents Ibias running in the unselected memory cells connected with the selected data line as denoted in Equation 1. The bias current Ibias is equal to a total of bias components Ibias0 in the unselected memory cells. However, R in Equation 1 represents a level of the resistance at the low resistance state of the unselected memory cell while n being the number of the bit lines. It is thus assumed that one of the bit lines is selected in every memory cell array. When all the unselected memory cells remain at the low resistance state, the current Ids is a maximum.
                                                        Ids              =                              Iw                +                Ibias                                                                                        =                              Iw                +                                  Ibias                  ⁢                                                                          ⁢                  0                  ×                                      (                                          n                      -                      1                                        )                                                                                                                          =                              Iw                +                                                      Vw                    /                                          (                                              2                        ×                        R                                            )                                                        ×                                      (                                          n                      -                      1                                        )                                                                                                          (                  Equation          ⁢                                          ⁢          1                )            
Assuming that the number of the bit lines is 16 in every memory cell array, the resistance R at the low resistance state of the unselected memory cells is 25Ω, and the write voltage is 3 V, the current Ids received by the selected data line and expressed in Equation 1 is denoted by
                                                        Ids              =                              Iw                +                                                      Vw                    /                                          (                                              2                        ×                        R                                            )                                                        ×                                      (                                          n                      -                      1                                        )                                                                                                                          =                              Iw                +                                  1.5                  ⁢                                                            (                      V                      )                                        /                    25                                    ⁢                                      (                                          k                      ⁢                                                                                          ⁢                      Ω                                        )                                    ×                  15                                                                                                        =                              Iw                +                                  900                  ⁢                                      (                    µA                    )                                                                                                          (                  Equation          ⁢                                          ⁢          2                )            
Accordingly, the current driving capability Itds required for the data line selecting transistors is higher than or equal to the current Ids as denoted by Inequation 3.Itds>Iw+900(μA)  (Inequation 3)
It is also assumed that the data line selecting transistors with their data lines are fabricated using a transistor width of 8F (F being the minimum unit in the manufacturing process). In case of 0.13 μm process, the transistor width of the data line selecting transistors is 1.04 μm creating the current driving capability of substantially 700 μA at best. This may hardly permit the current Ids to run through the selected data line. As the result, the conventional ½ bias mode fails to supply the selected data line with a proper level of the current, hence disabling the writing action with desired writing characteristics.
The conventional ⅓ bias mode will also be examined. FIG. 17 is a circuitry diagram showing an arrangement of data line selecting transistors TDS0 to TDS4 and bit line selecting transistors TBS0 to TBS4 connected with the data lines and the bit lines for applying the row selecting potential (Vw), the column selecting potential (e.g., 0 V), and the bias voltage (Vw/3, 2Vw/3) for inhibiting the writing action in the memory cell array at the conventional ⅓ bias mode shown in FIG. 13. The number of the data lines and the number of the bit lines may arbitrarily be determined. For example, the memory cell array includes a matrix of m rows by n columns (m and n being any natural numbers). The memory cell array shown in FIG. 17 has five rows and five columns.
Similarly in the writing action, the current Ids running in the selected data line (DL2 in FIG. 17) is a sum of the write current Iw running in the selected memory cell and the bias currents Ibias running in the unselected memory cells connected with the selected data line as denoted in Equation 4. The bias current Ibias is equal to a total of bias components Ibias0 in the unselected memory cells. However, R in Equation 4 represents a level of the resistance at the low resistance state of the unselected memory cell while n being the number of the bit lines. It is thus assumed that one of the bit lines is selected in every memory cell array. When all the unselected memory cells remain at the low resistance state, the current Ids is a maximum.
                                                        Ids              =                              Iw                +                Ibias                                                                                        =                              Iw                +                                  Ibias                  ⁢                                                                          ⁢                  0                  ×                                      (                                          n                      -                      1                                        )                                                                                                                          =                              Iw                +                                                      Vw                    /                                          (                                              3                        ×                        R                                            )                                                        ×                                      (                                          n                      -                      1                                        )                                                                                                          (                  Equation          ⁢                                          ⁢          4                )            
Assuming that the number of the bit lines is 16 in every memory cell array, the resistance R at the low resistance state of the unselected memory cells is 25Ω, and the write voltage Vw is 3 V, the current Ids received by the selected data line and expressed in Equation 4 is denoted by
                                                        Ids              =                              Iw                +                                                      Vw                    /                                          (                                              3                        ×                        R                                            )                                                        ×                                      (                                          n                      -                      1                                        )                                                                                                                          =                              Iw                +                                  1                  ⁢                                                            (                      V                      )                                        /                    25                                    ⁢                                      (                                          k                      ⁢                                                                                          ⁢                      Ω                                        )                                    ×                  15                                                                                                        =                              Iw                +                                  600                  ⁢                                      (                    µA                    )                                                                                                          (                  Equation          ⁢                                          ⁢          5                )            
Accordingly, the current driving capability Itds required for the data line selecting transistors is higher than or equal to the current Ids as denoted by Inequation 6.Itds>Iw+600(μA)  (Inequation 6)
It is also assumed that the data line selecting transistors with their data lines are fabricated using a transistor width of 8F (F being the minimum unit in the manufacturing process). In case of 0.13 μm process, the transistor width of the data line selecting transistors is 1.04 μm creating the current driving capability of substantially 700 μA at best. This may permit the drive current received by the target memory cell to be 100 μA or smaller with the current Ids running in the selected data line. As the result, the conventional ⅓ bias mode fails to supply the selected data line with a proper level of the current particularly when the transistor width of the data line selecting transistors is limited or the number of the bit lines in the memory cell array is increased, hence disabling the writing action with desired writing characteristics.
The above description is conditioned with the write current supplied from the data line to the target memory cell. The same drawback may however be expected when the write current is supplied from the bit line to the target memory cell or when the current supplying action of the data line is replaced by that of the bit line.
As explained, the writing action of Citation 1 fails to supply the target memory cell with a proper level of the write current when the variable resistor element in the variable resistance nonvolatile memory for varying its resistance with the application of electric pulses is fabricated of PCMO having a perovskite structure or OUM (ovonic memory) made of chalcogenide compound or metal oxide including a transition metal oxide such as NiO2, TiO2, HfO2, or ZrO2.
As for the relationship between the data line and the bit line at a cross point memory, it is a good idea for ensuring the same effect regardless of the write current supplied from either line that the numbers of rows and columns in the memory cell array are set equal to each other. However in the reading action, the read current determined by the resistance of the target memory cell is measured at either the data line or the bit line. This will discriminate the data line selecting transistors and the bit line selecting transistors from each other in the layout arrangement. In other words, either the data line selecting transistors or the bit line selecting transistors will comparatively be limited in the layout arrangement. For guaranteeing the write current to be supplied to the target memory cell, the current driving capability of the selecting transistors may be increased by expanding the layout arrangement. As the result, the memory size or chip area will be increased thus soaring the overall production cost.